|
FROM THE EDITOR
This week we pack up our programmable logic and head
into orbit with our "FPGAs
in Space" feature. If you think designing FPGAs is tough, take a
look at what happens when you leave the safe and happy environment
of Earth's atmosphere.
Next, we have a feature from Brock LaMeres of
Agilent on the use of serial I/O standards in FPGAs. High speed
serial promises higher data rates, fewer interconnect wires, and
greater system reliability. All these benefits don't come for free,
however, as serial I/O design poses unique challenges that must be
understood and conquered.
Thanks for reading! If
there's anything we can do to make our publications more useful to
you, please let us know at: comments@fpgajournal.com
Kevin
Morris – Editor
FPGA and Programmable Logic
Journal |
|
FPGAs in Space
Programmable Logic in Orbit
When was the last time you disassembled the package of
each FPGA in your design to make sure the bonding is secure? Would your
design criteria be different if shipping your device to its destination
cost $13,000.00 per pound? What if your FPGA was in an environment where
the radiation levels made random upsets of memory elements more the rule
than the exception? If your device were operating in a vacuum, how would
you think about heat dissipation? Would you work or think differently if
an error in your design could result in loss of life, or in property
damage in the hundreds of millions of dollars?
Welcome to the
world of programmable logic in space. While we may sometimes find it
difficult to get our designs to behave the way we envision here on the
ground, getting digital systems to perform well in space is another matter
altogether. The environmental challenges, the cost of deployment, and the
extreme risk of failure all conspire to create one of the most difficult
problems faced by digital designers today.
Overall, programmable
logic is a godsend for spacecraft electronics development. Building a
system from ASSPs or standard parts is seldom an option, due to the
limited availability of properly qualified devices, and also because the
cost of putting the system into orbit puts integration at a premium. Space
designs are never deployed in significant volume, so non-recurring
engineering (NRE) costs dominate any ASIC or custom device project
intended for space use. Additionally, an ASIC re-spin can cost weeks of
schedule time, and slipping launch schedules can cause enormous cost
overruns. FPGAs, with their zero NRE and relatively short design cycles,
are economically superior at virtually any unit price. Reconfigurable
programmable logic devices offer the added advantage of post-launch design
modification that could make the difference between a working system and
orbiting space junk. [more]
|
|
FPGA I/O
When to go Serial
by Brock J. LaMeres, Agilent Technologies
Over the past decade, FPGAs have gained a
foothold as one of the most used building blocks in digital systems. The
flexibility of an FPGA allows designers to decrease hardware design cycles
while adding inherent feature upgradability in the final product. In
addition, the data rates of modern FPGAs are competing with CMOS ASICs,
thus allowing the needed system performance to be achieved using what was
once only a proto-typing vehicle.
The data rates of modern FPGAs are giving
designers the freedom to create their own application specific busses.
However, designers are quickly learning the pitfalls of running I/O at
high speeds. Factors such as channel-to-channel skew, jitter, and aperture
window size are limiting the theoretical data rates of the FPGAs
specifications. To address these issues, FPGA system designers are
following suit to their ASIC predecessors and adopting I/O architectures
that inherently reduce the effect of the above-mentioned factors. [more]
|
